MCS-4 Instruction Set

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by XTREME104

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<h1>4004 Instruction Set</h1>
<h2>Basic Instructions (* = 2 Word Instructions)</h2>
<table border="1" cellpadding="4">
    <tr>
        <th>Hex</th>
        <th>Mnemonic</th>
        <th>OPR<br/>D3D2D1D0</th>
        <th>OPA<br/>D3D2D1D0</th>
        <th>Description</th>
    </tr>
    <tr>
        <td>00</td>
        <td>NOP</td>
        <td>0000</td>
        <td>0000</td>
        <td>No operation.</td>
    </tr>
    <tr>
        <td>1---</td>
        <td>*JCN</td>
        <td>0001<br/>A2A2A2A2</td>
        <td>C1C2C3C4<br/>D1D1D1D1</td>
        <td>Jump to ROM address A2A2A2A2 A1A1A1A1. (within the same ROM that contains this JCN instruction) if condition C1C2C3C4 is true. otherwise go to the next instruction in sequence.</td>
    </tr>
    <tr>
        <td>2---</td>
        <td>*FIM</td>
        <td>0010<br/>D2D2D2D2</td>
        <td>RRR0<br/>D1D1D1D1</td>
        <td>Fetch immediate (direct) from ROM Data D2D2D2D2 D1D1D1D1 to index register pair location RRR.</td>
    </tr>
    <tr>
        <td>3-</td>
        <td>FIN</td>
        <td>0011</td>
        <td>RRR0</td>
        <td>Fetch indirect from ROM. Send contents of index register pair location 0 out as an address. Data fetched is placed into register pair location RRR.</td>
    </tr>
    <tr>
        <td>3-</td>
        <td>JIN</td>
        <td>0011</td>
        <td>RRR1</td>
        <td>Jump indirect. Send contents of register pair RRR out as an address at A1 and A2 time in the instruction cycle.</td>
    </tr>
    <tr>
        <td>4---</td>
        <td>*JUN</td>
        <td>0100<br/>A2A2A2A2</td>
        <td>A3A3A3A3<br/>A1A1A1A1</td>
        <td>Jump unconditional to ROM address A3A3A3A3 A2A2A2A2 A1A1A1A1.</td>
    </tr>
    <tr>
        <td>5---</td>
        <td>*JMS</td>
        <td>0101<br/>A2A2A2A2</td>
        <td>A3A3A3A3<br/>A1A1A1A1</td>
        <td>Jump to subroutine ROM address A3A3A3A3 A2A2A2A2 A1A1A1A1. save old address (up 1 level in stack).</td>
    </tr>
    <tr>
        <td>6-</td>
     ...

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